CS4362-KQZ【PDF 3/42 页】IC DAC 6CH 114DB 192KHZ 48LQFP

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DS257F2

CS4362

SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT

(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)

Notes:

19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

21.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

100

kHz

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 19)

thdd

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc, trc

-1

Fall Time SCL and SDA

tfc, tfc

300

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

(Note 20)

tack

(Note 21)

256

---------------------

128

---------------------

------------------

t buf

hdst

lo w

hdd

high

t sud

Stop

S t a rt

SD A

SC L

irs

RS T

hdst

t sust

t susp

St a rt

Stop

R epe a t e d

t ack

Figure 3. Control Port Timing - IC Format

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